In an effort to drastically increase the density of memory devices that are fabricated with conventional semiconductor processes and are compatible with conventional complimentary metal oxide silicon (CMOS) technology, efforts have been directed to devices that combine normal photolithographic groundrule and sub-photolithographic groundrule dimensions. However, there is a “pattern-mismatch” when normal photolithographic groundrule and sub-photolithographic groundrule structures are used in the same structure. “Pattern-mismatch” can cause yield loss and imperfect connections. Therefore, there is a need for an interface device, memory device, memory device architecture and method of fabricating memory devices that use normal photolithographic groundrule and sub-photolithographic groundrule structures that avoids this type of “pattern-mismatch.”